1. Field of the Invention
The present invention relates to a design-for-testability technique for a semiconductor integrated circuit and, in particular, to a test circuit inserting method and a test circuit inserting apparatus.
2. Description of the Related Art
Design-for-testability techniques as typified by scan design are employed widely to attain a sufficiently high fault coverage in tests of semiconductor integrated circuits. However, with the increase in the circuit scale and the complexity of circuits, the processing time for generation of test patterns for attaining a desired fault coverage tends to increase. One countermeasure employed is a method of increasing the testability by inserting test points in a circuit.
In a conventional test circuit inserting method for a semiconductor integrated circuit, a model circuit is configured on a computer in such a manner that logic elements and signal lines are arranged in the same manner as in a test subject circuit. Fault coverage and fault prevention information of each signal line are obtained by performing a fault simulation by inputting test patterns to the model circuit. Test point insertion points are determined on the basis of those kinds of information and test circuits are inserted. (Refer to JP-A-2000-250946, for example).
FIG. 19 is a flowchart of a process of a conventional test circuit inserting method for a semiconductor integrated circuit. As shown in FIG. 19, circuit information is input at step S101, random pattern generation and a fault simulation are performed at step S102, whether fault coverage is sufficiently high is judged at step S103, and test points are inserted at step S104 if the fault coverage is sufficiently high, and circuit information is output at step S105.
If it is judged at step S103 that the fault coverage is not sufficiently high, test point insertion candidates are extracted at step S106. Whether candidates exist is judged at step S107, the candidates are selected at step S108, and test points are inserted virtually at step S109. A fault simulation is performed at step S110 and whether the fault coverage has increased is judged at step S111. If the fault coverage has increased, the current test point insertion points are registered at step S112. Then, step S107 and the following steps are executed again.
In the fault simulation at step S110, fault coverage and fault prevention information of each signal line are obtained and test point insertion points are determined on the basis of those kinds of information. With This method, a high fault coverage is obtained while preventing increase in chip size.
However, in the above method, test points are merely determined on the basis of fault coverage and fault prevention information that are obtained by a fault simulation and the layout-related aspect of insertion of test circuits is not taken into account. Therefore, the above method has a problem that wiring congestion is caused by insertion of test circuits, resulting in increase in chip size.